Protocol and Interface Agnostic Universal D2D Controller for HPC and Chiplets

Demand for die-to-die and chip-to-chip interfaces has been growing steadily in the past few years due to new applications in cloud/data centers, AI (training and edge applications), and High-Performance Computing (HPC). The demand is driven by the requirements of high throughput, low latency and low power in these applications. Advances in packaging technology are further helping the adoption of heterogeneous systems with chiplets/known-good-die(KGD) assembly to create solutions that require the evolution of a new kind of interface popularly known as “Die-to-Die” interfaces. read more

Author: Ketan Mehta | Date:18-01-2021

WEBINAR: Differentiated Edge AI with OpenFive and CEVA

OpenFive is hosting a webinar with CEVA on November 12th to talk about how OpenFive’s vision platform, leveraging CEVA vision and AI solutions. Which can get you to a differentiated solution for your product with as much or as little silicon participation on your part as you want. I talked briefly to Jeff VanWashenova (CEVA Sr. Dir of AI and Computer Vision) to get a sense of the opportunity. read more

Author:  Bernard Murphy, SemiWiki | Date: 10-11-2020

OpenFive’s Customizable Silicon-Focused Solutions

The demand for domain-specific silicon and workload-focused architecture is driven by several key factors. General-purpose processors used to be the workhorses for the majority of computing tasks. With transistor cost increasing, and the end of Dennard scaling, general-purpose processors have become very power-hungry and performance increases are hard to find from process technology alone – architecture plays a key role in workload acceleration. read more

Author: Dr. Shafy Eltoukhy, SVP & GM of OpenFive | Date:16-08-2020

Webinar: Build Your Next HBM2/2E Chip with SiFive

I have been watching the trend for quite some time now that many advanced FinFET designs today are actually 2.5D systems in package. All of these 2.5D silicon interposer-based designs have high-bandwidth memory (HBM) stacks on board. Often there are multiple memory stacks in both 4-high and 8-high configurations. If you follow what’s been called the “more than Moore” revolution associated with 2.5 and 3D design. read more

Author:  Mike Gianfagna | Date: 04-05-2020

Chip-to-Chip Communication for Enterprise and Cloud

I recently had the opportunity to attend a SemiWiki webinar entitled “Chip-to-Chip Communication for Enterprise and Cloud”. The webinar was presented by SiFive and explored chip-to-chip communication strategies for a variety of applications. In the first part of the webinar, Ketan Mehta, director of SoC IP product marketing at SiFive explored the uses of the Interlaken protocol. This specification has been around since 2007. read more

Author: Mike Gianfagna | Date:01-04-2020