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AI technology has enabled electronic devices with the ability to not only see, but also understand the world around it. It enables a wide range of applications such as; self driving cars, automated delivery robots drones, smart cities, augmented reality, intelligent home assistants, and much more. All of these require purpose-built SoCs to provide the optimal balance of performance and power. Learn how OpenFive's AI Vision Platform with CEVA's Vision and AI solutions can be customized for your end application.
With recent advances in packaging technology, it is possible to connect multiple dies on a single package. OpenFive’s D2D Controller provides end to end connection from one die to another. In this webinar, we will review the trade-offs between various connectivity options. We will also review the application of D2D in Chiplets and HPC to meet the designers’ latency and power targets.
SiFive Storage Solutions: How RISC-V and Custom Silicon Platforms Enable Smart Storage Architectures
Currently, there is a huge demand in the market for storage systems. Reliability, high endurance and robustness are the essential features, which are very much required for such systems. Therefore, SSD controller-based storage solutions are most preferred for data centers.Join us in this webinar to learn about how SiFive and our partners are driving innovations in silicon architectures for data center and enterprise systems. We will cover the storage market and technology trends, the importance of RISC-V and custom silicon in these applications, and case studies including an NVMe based RISC-V computational storage platform.
Join us for our next SiFive Connect webinar to learn more about the features of the HBM2/2E IP subsystem and how to implement the IP in an SoC. We’ll also address the market applications for HBM2/2E IP. SiFive’s HBM2/2E IP subsystem solution is architected and designed to provide the highest performance and flexibility for integrating high bandwidth memory (HBM) directly into next-generation ASIC and 2.5D SoC system-in-package (SiP) solutions. It supports the HBM2/2E JEDEC specification for a multitude of foundry technology nodes.
Interlaken chip-to-chip connectivity IP has been used for many years in networking and switching fabrics to move high throughput data between large chips. With advanced technology nodes, increasing chip sizes, and CPU cluster-based designs, Interlaken has found a unique spot as the protocol of choice for low latency, high throughput chip-to-chip connectivity. SiFive is extending its 8th generation of Interlaken IP with the introduction of Interlaken-Low Latency (LL) IP, which will enable low latency chip-to-chip connectivity in HPC, AI/ML, enterprise, and cloud applications. Interlaken-LL IP can provide up to 256Gbps of reliable and scalable throughput between two chips; whereas the standard Interlaken IP from SiFive provides throughput of up to 1.2Tbps.
Join us in this webinar to learn more about our USB 3.2 IP solution, including Retimer, for high-speed consumer applications. We will review the IP engineering features, operations, configurations, protocols and implementation guidelines in detail. SiFive’s USB 3.2 Gen2 Retimer IP cores are compliant with the USB 3.2 Appendix E standard. USB 3.2 Gen 2 supports up to 10 Gbps of bandwidth. It includes a USB 3.2 Gen2 single lane PCS layer and supports all low power states.